Field of the Invention
Embodiments of the present invention relate generally to three-dimensional (3D) graphics processing, and, more particularly, to distributed tiled caching.
Description of the Related Art
A system for rendering three-dimensional graphics typically receives commands that are provided by an application programmer and processes the commands to generate pixels for a display. Such systems generally include a world-space pipeline and a screen-space pipeline. The world-space pipeline processes primitives and transmits the processed primitives to the screen-space pipeline. The screen-space pipeline receives the primitives and generates final pixels for display. The screen-space pipeline processes primitives in application-programming-interface (API) order so that final pixel values are produced as expected by the application programmer. More specifically, the outputs of various units within a screen-space pipeline depend on the order in which those units process received primitives. If primitives were to be processed in an incorrect order, then the outputs of the screen-space pipeline, such as final color values, would be not as expected by the application programmer. Therefore, in order to produce results that are as expected by the application programmer, the primitives are processed in an order (“API order”) that is consistent with the commands provided by the application programmer.
Some graphics systems implement a tiling architecture in which a render target is divided into tiles. Work processed in such a graphics system is rearranged such that the work is processed in tile order. In other words, work associated with a first tile is processed first, then work associated with a second tile is processed, then work associated with a third tile, and so forth. Even with such architectures, work in the screen-space pipeline should be processed in API order for the reasons discussed above. Thus, a challenge when designing systems with tiling architectures is to configure the tiling unit and other units involved in generating the tile such that API order can be maintained in the screen-space pipeline.
In addition to the foregoing, more advanced tiling architectures may include multiple processing entities that are configured to implement different instances of a world-space pipeline and/or a screen-space pipeline. The sheer complexity of such highly parallel tiling architectures presents an even greater challenge to maintaining proper API order in the different screen-space pipelines.
As the foregoing illustrates, what is needed in the art is an approach for maintaining API order in the screen-space pipeline(s) of a highly parallel tiling architecture.